International Journal of Applied Mathematics and Machine Learning[1] V. Dubey and R. Sairam, An arithmetic and logic unit optimized for
area and power, in International Conference on Advanced Computing and
Communication Technologies (2014), 330-334.
DOI: https://doi.org/10.1109/ACCT.2014.70
[2] G. Ramana Murthy, C. Senthilpari, P. Velrajkumar and T. S. Lim, A
new 6-T multiplexer based full-adder for low power and leakage current
optimization, IEICE Electronics Express 9(17) (2012), 1434-1441.
DOI: https://doi.org/10.1587/elex.9.1434
[3] J. Rabaey, Low Power Design Essentials, 1st Edition, Springer
Publishing Company, Incorporated, 2009.
DOI: https://doi.org/10.1007/978-0-387-71713-5
[4] J. Sun and A. Jiang, The power dissipation comparison of different
ALU architectures, International Conference on Mechanical and
Electrical Technology (2010), 430-433.
DOI: https://doi.org/10.1109/ICMET.2010.5598395
[5] Omnia Ali Albadry, M. A. Mohamed El-Bendary, Fathy Z. Amer and
Said M. Singy, Design of area efficient and low power 4-bit multiplier
based on full- swing GDI technique, International Conference on
Innovative Trends in Computer Engineering (ITCE), 2019.
DOI: https://doi.org/10.1109/ITCE.2019.8646341
[6] Chua-Chin Wang, Nanang Sulistiyanto, Tsung-Yi Tsai and Yu-Hsuan
Chen, Multifunctional in-memory computation architecture using
single-ended disturb-free 6T SRAM, Springer Nature Singapore Pvt.
Ltd., Advances in Electronics Engineering, Lecture Notes in Electrical
Engineering 619 (2020), 49-57.
DOI: https://doi.org/10.1007/978-981-15-1289-6_5
[7] Sombathini Rachana, Nandyala Ramanjulu and P. Krishna Murthy,
Design of area efficient and low power 4-bit multiplier based on TG,
International Journal of Emerging Technologies and Innovative Research
7(12) (2020), 83-88.
[8] G. Harshitha, E. J. Kishore, R. Manoj, Priyanka R. Devarmani, Y.
G. Praveen Kumar and M. Z. Kurian, Gate-diffusion input based linear
feedback shift register: A review, in International Conference on
Smart Systems and Inventive Technology, 2019.
DOI: https://doi.org/10.1109/ICSSIT46314.2019.8987975
[9] M. Anis, M. Allam and M. Elmasry, Impact of technology scaling on
CMOS logic styles, IEEE Transactions on Circuits and Systems II:
Analog and Digital Signal Processing 49(8) (2002), 577-588.
DOI: https://doi.org/10.1109/TCSII.2002.805631
[10] A. Morgenshtein, A. Fish and I. A. Wagner, Gate-diffusion input
(GDI) - A novel power efficient method for digital circuits: A design
methodology, in Proceedings 14th Annual IEEE International ASIC/SOC
Conference (IEEE Cat. No.01TH8558) (2001), 39-43.
DOI: https://doi.org/10.1109/ASIC.2001.954670
[11] A. Morgenshtein, A. Fish and I. A. Wagner, Gate-diffusion input
(GDI): A power-efficient method for digital combinatorial circuits,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(5)
(2002), 566-581.
DOI: https://doi.org/10.1109/TVLSI.2002.801578
[12] M. Kumar, M. A. Hussain and L. L. K. Singh, Design of a low power
high speed ALU in 45nm using GDI technique and its performance
comparison, in Communications in Computer and Information Science 142
(2011), 458-463.
DOI: https://doi.org/10.1007/978-3-642-19542-6_87
[13] P.-M. Lee, C.-H. Hsu and Y.-H. Hung, Novel 10-T full adders
realized by GDI structure, International Symposium on Integrated
Circuits (2007), 115-118.
DOI: https://doi.org/10.1109/ISICIR.2007.4441810
[14] F. Moradi, D. T. Wisland, H. Mahmoodi, S. Aunet, T. V. Cao and A.
Peiravi, Ultra low power full adder topologies, IEEE International
Symposium on Circuits and Systems (2009), 3158-3161.
DOI: https://doi.org/10.1109/ISCAS.2009.5118473
[15] A. Morgenshtein, A. Fish and I. A. Wagner, An efficient
implementation of D-flip-flop using the GDI technique, IEEE
International Symposium on Circuits and Systems (IEEE Cat.
No.04CH37512) 2 (2004), II-673.
DOI: https://doi.org/10.1109/ISCAS.2004.1329361
[16] A. Morgenshtein, I. Shwartz and A. Fish, Gate diffusion input
(GDI) logic in standard CMOS nanoscale process, IEEE 26th Convention
of Electrical and Electronics Engineers in Israel (2010), 776-780.
DOI: https://doi.org/10.1109/EEEI.2010.5662107
[17] R. Uma and P. Dhavachelvan, Modified gate diffusion input
technique: A new technique for enhancing performance in full adder
circuits, Procedia Technology 6 (2012), 74-81.
DOI: https://doi.org/10.1016/j.protcy.2012.10.010
[18] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design,
2009.
[19] Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi,
Rob A. Rutenbar and Kenneth L. Shepard, Digital circuit design
challenges and opportunities in the Era of Nanoscale CMOS, Proceedings
of the IEEE 96(2) (2008), 343-365.
DOI: https://doi.org/10.1109/JPROC.2007.911072
[20] V. R. Tirumalasetty and M. R. Machupalli, Design and analysis of
low power high-speed 1-bit full adder cells for VLSI applications,
International Journal of Electronics 106(4) (2019), 521-536.
DOI: https://doi.org/10.1080/00207217.2018.1545256
[21] B. N. Vegha and Dr. Vijay Prakash, Design and implementation of
4-bit ALU for low-power using adiabatic logic based on FINFET,
International Journal of Engineering Research and Technology 9(7)
(2020), 649-656.
DOI: https://doi.org/10.17577/IJERTV9IS070238
[22] W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya,
Pass-transistor logic design, International Journal of Electronics
70(4) (1991), 739-749.
DOI: https://doi.org/10.1080/00207219108921324
[23] D. Wang, M. Yang, W. Cheng, X. Guan, Z. Zhu and Y. Yang, Novel
low power full adder cells in 180nm CMOS technology, IEEE Conference
on Industrial Electronics and Applications (2009), 430-433.
DOI: https://doi.org/10.1109/ICIEA.2009.5138242
[24] Rimjhim Saxena and Kiran Sharma, Delay optimization and power
optimization of 4-bit ALU designed in FS-GDI technique, Smart Moves
Journal Ijoscience 6(2) (2020), 1-12.
DOI: https://doi.org/10.24113/ijoscience.v6i2.264
[25] M. Shoba and R. Nakkeeran, GDI based full adders for energy
efficient arithmetic applications, Engineering Science and Technology,
an International Journal 19(1) (2016), 485-496.
DOI: https://doi.org/10.1016/j.jestch.2015.09.006
[26] T. E. Rani, M. A. Rani and R. Rao, AREA optimized low power
arithmetic and logic unit, in 3rd International Conference on
Electronics Computer Technology 3 (2011), 224-228.
DOI: https://doi.org/10.1109/ICECTECH.2011.5941742
[27] K. Nehru, A. Shanmugam and G. Darmila Thenmozhi, Design of low
power ALU using 8T FA and PTL based MUX circuits, IEEE-International
Conference on Advances in Engineering, Science and Management (2012),
145-149.
[28] R. L. Shukla and R. Mehra, Design analysis and simulation of 1
bit arithmetic logic unit on different Foundaries, International
Journal of Science and Engineering 2(1) (2013), 44-53.
[29] Mehedi Hasan, Md. Jobayer Hossein, Mainul Hossain, Hasan U. Zaman
and Sharnali Islam, Design of a scalable low-power 1-bit hybrid full
adder for fast computation, Circuits and Systems II: Express Briefs,
IEEE Transactions on Circuits and Systems II: Express Briefs 67(8)
(2020), 1464-1468.
DOI: https://doi.org/10.1109/TCSII.2019.2940558
[30] Kishore Sanapala and Ramachandran Sakthivel, Ultra-low-voltage
GDI-based hybrid full adder design for area and energy-efficient
computing systems, IET Circuits, Devices & Systems 13(4) (2019),
445-470.
DOI: https://doi.org/10.1049/iet-cds.2018.5559
[31] G. S. Reddy and K. V. K. Rao, 32 – bit arithmetic and
logic unit design with optimized area and less power consumption by
using GDI technique, International Journal of Research in Computer
Applications and Robotics 3(4) (2015), 51-66.
[32] N. Ravindran and R. M. Lourde, An optimum VLSI design of a 16-BIT
ALU, International Conference on Information and Communication
Technology Research (2015), 52-55.
DOI: https://doi.org/10.1109/ICTRC.2015.7156419
[33] J. Nandini and V. V. M. Krishna, Design of 64-bit low power ALU
for DSP applications, International Journal of Research Trends in
Engineering and Technology I(V) (2016), 244-248.
[34] M. Mukhedkar and W. B. Pandurang, A 180nm efficient low power and
optimized area ALU design using gate diffusion input technique,
International Conference on Data Management, Analytics and Innovation
(2017), 47-51.
DOI: https://doi.org/10.1109/ICDMAI.2017.8073484
[35] B. S. Ryu, J. S. Yi, K. Y. Lee and T. W. Cho, A design of low
power 16-b ALU, in Proceedings of IEEE. IEEE Region 10 Conference.
TENCON 99, Multimedia Technology for Asia-Pacific Information
Infrastructure (Cat. No.99CH37030), 2 (1999), 868-871.
DOI: https://doi.org/10.1109/TENCON.1999.818556
[36] C.-K. Tung, S.-H. Shieh and C.-H. Cheng, Low-power high-speed
full adder for portable electronic applications, Electronics Letters
49(17) (2013), 1063-1064.
DOI: https://doi.org/10.1049/el.2013.0893
[37] T. Bhagyalaxmi, S. Rajendar and S. Srinivas, Power-aware
alternative adder cell structure using swing restored complementary
pass transistor logic at 45nm technology, Procedia Materials Science
10 (2015), 789-792.
DOI: https://doi.org/10.1016/j.mspro.2015.06.021
[38] P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, and A. Dandapat,
Performance analysis of a low-power high-speed hybrid 1-bit full adder
circuit, IEEE Transactions on Very Large Scale Integration Systems
23(10) (2015), 2001-2008.
DOI: https://doi.org/10.1109/TVLSI.2014.2357057
[39] P. Kumar and R. K. Sharma, An energy efficient logic approach to
implement CMOS full adder, Journal of Circuits, Systems and Computers
26(05) (2017); Article 1750084.
DOI: https://doi.org/10.1142/S0218126617500840
[40] M. Amini-Valashani, M. Ayat and S. Mirzakuchaki, Design and
analysis of a novel low-power and energy-efficient 18T hybrid full
adder, Microelectronics Journal 74 (2018) 49-59.
DOI: https://doi.org/10.1016/j.mejo.2018.01.018
[41] O. Al Badry and M. A. Abdelghany, Low power 1-bit full adder
using full-swing gate diffusion input technique, International
Conference on Innovative Trends in Computer Engineering (2018),
205-208.
DOI: https://doi.org/10.1109/ITCE.2018.8316625
[42] O. A. Al Badry, M. A. M. El-Bendary, F. Z. Amer and S. M. Singy,
Design of area efficient and low power 4-bit multiplier based on full
swing GDI technique, International Conference on Innovative Trends in
Computer Engineering 1(1) (2019), 2-4.
DOI: https://doi.org/10.1109/ITCE.2019.8646341
